Description
Tutor Marked Assignment
DIGITAL AND ANALOG CIRCUITS AND INSTRUMENTATION
Course Code: BPHET-143
Assignment Code: BPHET-143/TMA/2025
Max. Marks: 100
Note: Attempt all questions. The marks for each question are indicated against it.
PART A
1. a) Describe the formation of depletion layer in a p-n junction diode. Explain the I-V
characteristics of p-n junction in forward and reversed biased conditions. (5)
b) The intrinsic carrier concentration of a semiconductor is 3 17m 10 3 . It is doped
with a trivalent impurity with dopant atom density of 3 18m 10 8 . The electron and
hole mobilities are 1 1 2 s V m 5 . 0 and 1 1 2 s V m 3 . 0 respectively. Calculate its
conductivity before and after the doping. (5)
2. a) Explain the working of p-channel JFET using a circuit diagram showing its voltage
biasing with appropriate polarities. Draw its drain characteristics with VDS < 0 V
and VGS 0 V. (4+2)
b) Discuss the breakdown mechanisms observed in a zener diode. (4)
c) h-parameters of a single stage CE amplifier are given as hi = 2 k , hr = 3 104,
hf = 85 and ho = 15 AV1. Calculate Ai, Av, Zin and Zout with rL = 10 k and
rS = 100 . (5)
3. a) Convert FC16 (Hex) into its binary equivalent and then divide it by 10012. Express
the result in octal equivalent. (5)
b) Draw the circuit of 2-input NAND gate using diodes, transistor and resistors and
explain its working with the help of truth table. (5)
4. a) Design a binary adder circuit to add 4-bit binary numbers corresponding to the
decimal numbers 11 and 7. (5)
b) Construct the Karnaugh map for the following 3-input truth table, write its Boolean
expression and simplify it to obtain MSP. (3+1+1)
A B C Y
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
(5)
c) With the help of a suitable diagram, explain the subtraction of binary equivalent of
decimal number 5 from binary equivalent of decimal number 7 using a 2’s
complement binary adder-subtractor.
PART B
5. a) Why is a Class A amplifier preferred over Class C amplifier in spite of being less
efficient?
b) Why is it necessary to use matched pair of transistors in a push-pull amplifier?
c) An amplifier has maximum voltage gain of 500. Express it in dB scale. Calculate
the gain at the cut-off frequencies on dB scale.
d) What are the advantages of transformer coupling between the two stages of a
cascade amplifier?
6. a) State the Barkhausen criterion for sustained oscillations. Explain the operation of
Colpitt Oscillator. For a Colpitt oscillator with 10 MHz frequency determine the
equivalent capacitance, C forming tank circuit with 0.1 mH inductor.
b) In a voltage regulator circuit, the output voltage under no load condition is 12V
while under full load it is 11.8V. Over the full range of input voltage variation the
nominal voltage output of 12V varies by 50 mV. Calculate percentage load and line
regulation.
c) Design and draw a circuit of series pass voltage regulator to provide 25 V output
voltage and 160 mA maximum load current using a silicon n-p-n transistor with
=80. Assume the input unregulated voltage to be 30 V and minimum zener diode
current to be 10 mA. Specify the voltage and power rating of zener diode as well
as value and power rating of the resistor used.
7. a) Draw a circuit of a non-inverting amplifier with gain 1 using op-amp. Draw the
output voltage curve of this circuit for a step input of 5V amplitude and 50 kHz
frequency, if the slew rate of the op-amp is 0.5 V/s. (Use proper scale on the time
axis to illustrate the effect of slew rate).
b) Design and draw the circuit of a three channel op-amp adder with channel gains of
5, 10 and 15 respectively.
c) Explain the terms CMRR and input offset voltage in case of op-amp.
8. a) State the main subsystems of a CRO and explain their functions.
b) Design an astable multivibrator using IC 555 timer to generate a rectangular wave
of 60% duty cycle at 10 kHz frequency.
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